Japanese Laid-open Patent Publication No. 2009-9570 discusses a cascaded delayed execution pipeline to maintain a precise machine state. A delay of one or more cycles is inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Since a precise machine state is maintained, error detection and recovery mechanisms are built directly into register files of a system. If an error is detected, execution of an instruction associated with the error and all subsequent instructions is restarted.
Japanese Laid-open Patent Publication No. 7-160587 discusses a redundant memory device. The memory device includes a parity circuit configured to detect a single-bit error when data is read, a selecting circuit configured to, when a single-bit error is detected, select and use data in a normal memory unit included in the redundant memory device in order to continue a process, and a duplicate data comparing circuit configured to detect an error of two or more bits. In an initial inspection, if a fixed failure of two or more bits associated with one system included in the redundant memory device is detected, an address in the memory unit associated with the failure is indicated as invalid or valid. The duplicate data comparing circuit is disabled in response to an address invalid signal. Data in a system having addresses which are indicated as valid by a unit configured to indicate an address as invalid or valid and in which any parity error has not been detected is indicated to be used.
Japanese Laid-open Patent Publication No. 5-88990 discusses a redundant memory device which avoids the occurrence of a two-bit error or the like due to accumulation of soft errors in memory units and thus exhibits high reliability. A given time interval is set in a timer. A bus arbiter receives a check request output from the timer at given time intervals and protects first and second memory units included in the redundant memory device against access from a central processing unit (CPU).
An address generator is activated in response to the check request from the timer and generates addresses to scan all of areas in the first and second memory units. A parity check unit checks the parity of data read from each address of the first and second memory units. When the parity check unit detects an error, an error correcting unit writes correct data into an area in the memory unit associated with the detected error.
If a bit error occurs due to a soft error or the like in a memory unit in a state machine, the bit error may be detected by a parity check but the error is not corrected. Disadvantageously, an operation of the state machine is not continued after the occurrence of the error.
In the redundant memory device discussed in Japanese Laid-open Patent Publication No. 7-160587, a normally operating memory unit is selected and used. Disadvantageously, if an error occurs in this memory unit, the process is not continued.
In the redundant memory device discussed in Japanese Laid-open Patent Publication No. 5-88990, the first and second memory units are arranged for redundant memory and the parity check and error correction are performed at given time intervals. If an error occurs between parity check cycles, the memory unit associated with the error remains in an erroneous state until the next parity check. Disadvantageously, values in the memory unit are not correct at any time. If data is read from the memory unit during the period between the occurrence of the error and the correction thereof, an abnormal value may be processed.